Power-on reset circuits are widely used in integrated circuit devices to generate a reset signal. Typically they generate a high reset signal, usually equal to the value of the positive voltage supply, during part of the time the supply voltage is rising from zero volts to the final operating voltage, and as the supply voltage reaches an acceptable value, they return the reset signal to a low signal so that operation of the integrated circuit can begin. Power-on reset circuits also generate a reset signal if the supply voltage falls sufficiently during operation that circuit operation might be improper.
Prior power-on reset circuits have several disadvantages:
1) During operation, the power-on reset circuit draws power. PA1 2) In some power-on reset circuits there is no supply voltage threshold detection. The POR signal is released after a certain amount of time regardless of the voltage supply level. If the supply voltage is too low, incorrect circuit operation may result. PA1 3) The length of time the reset pulse is asserted depends to a considerable extent upon the voltage supply rise time, and may not be sufficient to assure that the power supply voltage has had time to stabilize. PA1 4) Some power-on reset circuits do not reliably generate reset pulses if there is a quick power cycle, that is, if voltage is brought to zero and quickly back to normal level.
FIG. 1 shows a prior art power-on reset circuit 11 such as illustrated by Wong et al., at page 769 in the article "Zero-Power 25-ns CMOS EPLD's" published in the IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October 1986. Capacitive node N1 drives inverter I1 and is driven by inverter I2. When the supply voltage Vcc is lowered to ground level, capacitor C1 is discharged through diode D1, which is formed by the P-channel transistor of inverter I2. Since diode D1 turns off when the voltage difference between N1 and Vcc is less than about 0.7 volts, capacitor C1 does not discharge below about 0.7 volts. Over time, capacitor C1 will continue to discharge through leakage. However, if the supply voltage is brought high again while capacitive node N1 is still at about 0.7 volts, inverter I1 will interpret its input node as a high voltage (N1 is higher than Vcc) and will generate a low output voltage. Thus power-on reset circuit 11 will fail to generate a high reset signal POR.
FIG. 2 shows another prior art power-on reset circuit discussed in Harrington, U.S. Pat. Nos. 5,166,545 FIGS. 4A6 and 4A6a. Since transistor 202 will turn on as soon as the supply voltage reaches one NMOS threshold voltage (about 0.7 volts), it is possible for the POR signal to be turned off while the supply voltage is at an unsafely low level.
FIG. 3 shows another prior art power-on reset circuit shown in FIG. 8 of Ogawa, et al. U.S. Pat. No. 5,177,375. Ogawa discloses a device which uses a P-channel transistor Q11 to provide a discharge path when power goes to a low value. The voltage at node 1 will be brought to about 0.7 volts through P-channel transistor Q11, but since Ogawa's inverter 25 is not a high threshold inverter, this 0.7 volts will be interpreted as a logical 1 when power again begins to rise, so a short power drop does not cause the device of FIG. 8 of Ogawa to generate a reset signal.
As mentioned above, another weakness of prior art devices is the consumption of power during operation of the chip. FIG. 4 shows a circuit disclosed in U.S. Pat. 5,109,163 to Benhamida, which does find a method of discharging a reference node to ground in response to a fast drop in power, but in FIG. 4 a current path exists from the positive voltage supply at node 12 to ground during operation of the circuit. To respond to a quick power drop, node A is discharged to ground by transistor Q3 in response to power again rising, and provides a low signal to inverter 18, which provides a high output signal at node B, turning on transistor Q4. Transistor Q4 therefore pulls node C to ground so that when power continues to rise, the low voltage at node C causes a reset signal to be generated. However, during operation there is a current path to ground from node 12 through node A, and thus this circuit draws power during circuit operation.
It is desirable to provide a power-on reset circuit which overcomes the above disadvantages.